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TrapConfig.cxx
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1// Copyright 2019-2020 CERN and copyright holders of ALICE O2.
2// See https://alice-o2.web.cern.ch/copyright for details of the copyright holders.
3// All rights not expressly granted are reserved.
4//
5// This software is distributed under the terms of the GNU General Public
6// License v3 (GPL Version 3), copied verbatim in the file "COPYING".
7//
8// In applying this license CERN does not waive the privileges and immunities
9// granted to it by virtue of its status as an Intergovernmental Organization
10// or submit itself to any jurisdiction.
11
13// //
14// TRAP config //
15// //
16// Author: J. Klein (Jochen.Klein@cern.ch) (run2 version //
17// S. Murray (murrays@cern.ch) //
19
20#include "TRDBase/Geometry.h"
21#include "TRDBase/FeeParam.h"
22#include "TRDSimulation/TrapConfig.h"
23#include "DataFormatsTRD/Constants.h"
24#include <fairlogger/Logger.h>
25
26#include <fstream>
27#include <iostream>
28#include <iomanip>
29#include <array>
30
31using namespace std;
32using namespace o2::trd;
33using namespace o2::trd::constants;
34
35bool TrapConfig::mgRegAddressMapInitialized = false;
36
37const std::array<int, TrapConfig::mlastAlloc> o2::trd::TrapConfig::TrapValue::mgkSize = {0, 1, 540, 1080, 8 * 18 * 540, 4, 6, 8 * 18 * 30};
38
39TrapConfig::TrapConfig()
40{
41 // default constructor
42
43 // initialize and reset the TRAP registers
44 initRegs();
45 resetRegs();
46
47 for (int iWord = 0; iWord < mgkDmemWords; ++iWord) {
48 mDmem[iWord].setAddress(iWord + mgkDmemStartAddress);
49 }
50
51 // initialize the map from address to register
52 if (!mgRegAddressMapInitialized) {
53 for (int iReg = 0; iReg < kLastReg; iReg++) {
54 int addr = mRegisterValue[iReg].getAddr();
55 if (addr < mgkRegisterAddressBlockStart[0]) {
56 LOG(error) << "Register address 0x" << hex << std::setw(4) << addr << " not handled in register map";
57 } else if (addr < mgkRegisterAddressBlockStart[0] + mgkRegisterAddressBlockSize[0]) {
58 mgRegAddressMap[addr - mgkRegisterAddressBlockStart[0]] = (TrapReg_t)iReg;
59 } else if (addr < mgkRegisterAddressBlockStart[1]) {
60 LOG(error) << "Register address 0x" << hex << setw(4) << addr << " not handled in register map";
61 } else if (addr < mgkRegisterAddressBlockStart[1] + mgkRegisterAddressBlockSize[1]) {
62 mgRegAddressMap[addr - mgkRegisterAddressBlockStart[1] + mgkRegisterAddressBlockSize[0]] = (TrapReg_t)iReg;
63 } else if (addr < mgkRegisterAddressBlockStart[2]) {
64 LOG(error) << "Register address 0x" << hex << setw(4) << addr << " not handled in register map";
65 } else if (addr < mgkRegisterAddressBlockStart[2] + mgkRegisterAddressBlockSize[2]) {
66 int ind = addr - mgkRegisterAddressBlockStart[2] + mgkRegisterAddressBlockSize[1] + mgkRegisterAddressBlockSize[0];
67 mgRegAddressMap[ind] = (TrapReg_t)iReg;
68 } else {
69 LOG(error) << "Register address 0x" << hex << setw(4) << addr << " not handled in register map";
70 }
71 }
72 mgRegAddressMapInitialized = true;
73 }
74}
75
76TrapConfig::~TrapConfig() = default;
77
78void TrapConfig::initRegs()
79{
80 // initialize all TRAP registers
81
82 // Name Address Nbits Reset Value
83 mRegisterValue[kSML0].init("SML0", 0x0A00, 15, 0x4050); // Global state machine
84 mRegisterValue[kSML1].init("SML1", 0x0A01, 15, 0x4200);
85 mRegisterValue[kSML2].init("SML2", 0x0A02, 15, 0x4384);
86 mRegisterValue[kSMMODE].init("SMMODE", 0x0A03, 16, 0xF0E2);
87 mRegisterValue[kSMCMD].init("SMCMD", 0x0A04, 16, 0x0000);
88 mRegisterValue[kNITM0].init("NITM0", 0x0A08, 14, 0x3FFF);
89 mRegisterValue[kNITM1].init("NITM1", 0x0A09, 14, 0x3FFF);
90 mRegisterValue[kNITM2].init("NITM2", 0x0A0A, 14, 0x3FFF);
91 mRegisterValue[kNIP4D].init("NIP4D", 0x0A0B, 7, 0x7F);
92 mRegisterValue[kCPU0CLK].init("CPU0CLK", 0x0A20, 5, 0x07);
93 mRegisterValue[kCPU1CLK].init("CPU1CLK", 0x0A22, 5, 0x07);
94 mRegisterValue[kCPU2CLK].init("CPU2CLK", 0x0A24, 5, 0x07);
95 mRegisterValue[kCPU3CLK].init("CPU3CLK", 0x0A26, 5, 0x07);
96 mRegisterValue[kNICLK].init("NICLK", 0x0A28, 5, 0x07);
97 mRegisterValue[kFILCLK].init("FILCLK", 0x0A2A, 5, 0x07);
98 mRegisterValue[kPRECLK].init("PRECLK", 0x0A2C, 5, 0x07);
99 mRegisterValue[kADCEN].init("ADCEN", 0x0A2E, 5, 0x07);
100 mRegisterValue[kNIODE].init("NIODE", 0x0A30, 5, 0x07);
101 mRegisterValue[kNIOCE].init("NIOCE", 0x0A32, 6, 0x21); // bit 5 is status bit (read-only)!
102 mRegisterValue[kNIIDE].init("NIIDE", 0x0A34, 5, 0x07);
103 mRegisterValue[kNIICE].init("NIICE", 0x0A36, 5, 0x07);
104 mRegisterValue[kARBTIM].init("ARBTIM", 0x0A3F, 4, 0x0); // Arbiter
105 mRegisterValue[kIA0IRQ0].init("IA0IRQ0", 0x0B00, 12, 0x000); // IVT om CPU0
106 mRegisterValue[kIA0IRQ1].init("IA0IRQ1", 0x0B01, 12, 0x000);
107 mRegisterValue[kIA0IRQ2].init("IA0IRQ2", 0x0B02, 12, 0x000);
108 mRegisterValue[kIA0IRQ3].init("IA0IRQ3", 0x0B03, 12, 0x000);
109 mRegisterValue[kIA0IRQ4].init("IA0IRQ4", 0x0B04, 12, 0x000);
110 mRegisterValue[kIA0IRQ5].init("IA0IRQ5", 0x0B05, 12, 0x000);
111 mRegisterValue[kIA0IRQ6].init("IA0IRQ6", 0x0B06, 12, 0x000);
112 mRegisterValue[kIA0IRQ7].init("IA0IRQ7", 0x0B07, 12, 0x000);
113 mRegisterValue[kIA0IRQ8].init("IA0IRQ8", 0x0B08, 12, 0x000);
114 mRegisterValue[kIA0IRQ9].init("IA0IRQ9", 0x0B09, 12, 0x000);
115 mRegisterValue[kIA0IRQA].init("IA0IRQA", 0x0B0A, 12, 0x000);
116 mRegisterValue[kIA0IRQB].init("IA0IRQB", 0x0B0B, 12, 0x000);
117 mRegisterValue[kIA0IRQC].init("IA0IRQC", 0x0B0C, 12, 0x000);
118 mRegisterValue[kIRQSW0].init("IRQSW0", 0x0B0D, 13, 0x1FFF);
119 mRegisterValue[kIRQHW0].init("IRQHW0", 0x0B0E, 13, 0x0000);
120 mRegisterValue[kIRQHL0].init("IRQHL0", 0x0B0F, 13, 0x0000);
121 mRegisterValue[kIA1IRQ0].init("IA1IRQ0", 0x0B20, 12, 0x000); // IVT om CPU1
122 mRegisterValue[kIA1IRQ1].init("IA1IRQ1", 0x0B21, 12, 0x000);
123 mRegisterValue[kIA1IRQ2].init("IA1IRQ2", 0x0B22, 12, 0x000);
124 mRegisterValue[kIA1IRQ3].init("IA1IRQ3", 0x0B23, 12, 0x000);
125 mRegisterValue[kIA1IRQ4].init("IA1IRQ4", 0x0B24, 12, 0x000);
126 mRegisterValue[kIA1IRQ5].init("IA1IRQ5", 0x0B25, 12, 0x000);
127 mRegisterValue[kIA1IRQ6].init("IA1IRQ6", 0x0B26, 12, 0x000);
128 mRegisterValue[kIA1IRQ7].init("IA1IRQ7", 0x0B27, 12, 0x000);
129 mRegisterValue[kIA1IRQ8].init("IA1IRQ8", 0x0B28, 12, 0x000);
130 mRegisterValue[kIA1IRQ9].init("IA1IRQ9", 0x0B29, 12, 0x000);
131 mRegisterValue[kIA1IRQA].init("IA1IRQA", 0x0B2A, 12, 0x000);
132 mRegisterValue[kIA1IRQB].init("IA1IRQB", 0x0B2B, 12, 0x000);
133 mRegisterValue[kIA1IRQC].init("IA1IRQC", 0x0B2C, 12, 0x000);
134 mRegisterValue[kIRQSW1].init("IRQSW1", 0x0B2D, 13, 0x1FFF);
135 mRegisterValue[kIRQHW1].init("IRQHW1", 0x0B2E, 13, 0x0000);
136 mRegisterValue[kIRQHL1].init("IRQHL1", 0x0B2F, 13, 0x0000);
137 mRegisterValue[kIA2IRQ0].init("IA2IRQ0", 0x0B40, 12, 0x000); // IVT om CPU2
138 mRegisterValue[kIA2IRQ1].init("IA2IRQ1", 0x0B41, 12, 0x000);
139 mRegisterValue[kIA2IRQ2].init("IA2IRQ2", 0x0B42, 12, 0x000);
140 mRegisterValue[kIA2IRQ3].init("IA2IRQ3", 0x0B43, 12, 0x000);
141 mRegisterValue[kIA2IRQ4].init("IA2IRQ4", 0x0B44, 12, 0x000);
142 mRegisterValue[kIA2IRQ5].init("IA2IRQ5", 0x0B45, 12, 0x000);
143 mRegisterValue[kIA2IRQ6].init("IA2IRQ6", 0x0B46, 12, 0x000);
144 mRegisterValue[kIA2IRQ7].init("IA2IRQ7", 0x0B47, 12, 0x000);
145 mRegisterValue[kIA2IRQ8].init("IA2IRQ8", 0x0B48, 12, 0x000);
146 mRegisterValue[kIA2IRQ9].init("IA2IRQ9", 0x0B49, 12, 0x000);
147 mRegisterValue[kIA2IRQA].init("IA2IRQA", 0x0B4A, 12, 0x000);
148 mRegisterValue[kIA2IRQB].init("IA2IRQB", 0x0B4B, 12, 0x000);
149 mRegisterValue[kIA2IRQC].init("IA2IRQC", 0x0B4C, 12, 0x000);
150 mRegisterValue[kIRQSW2].init("IRQSW2", 0x0B4D, 13, 0x1FFF);
151 mRegisterValue[kIRQHW2].init("IRQHW2", 0x0B4E, 13, 0x0000);
152 mRegisterValue[kIRQHL2].init("IRQHL2", 0x0B4F, 13, 0x0000);
153 mRegisterValue[kIA3IRQ0].init("IA3IRQ0", 0x0B60, 12, 0x000); // IVT om CPU3
154 mRegisterValue[kIA3IRQ1].init("IA3IRQ1", 0x0B61, 12, 0x000);
155 mRegisterValue[kIA3IRQ2].init("IA3IRQ2", 0x0B62, 12, 0x000);
156 mRegisterValue[kIA3IRQ3].init("IA3IRQ3", 0x0B63, 12, 0x000);
157 mRegisterValue[kIA3IRQ4].init("IA3IRQ4", 0x0B64, 12, 0x000);
158 mRegisterValue[kIA3IRQ5].init("IA3IRQ5", 0x0B65, 12, 0x000);
159 mRegisterValue[kIA3IRQ6].init("IA3IRQ6", 0x0B66, 12, 0x000);
160 mRegisterValue[kIA3IRQ7].init("IA3IRQ7", 0x0B67, 12, 0x000);
161 mRegisterValue[kIA3IRQ8].init("IA3IRQ8", 0x0B68, 12, 0x000);
162 mRegisterValue[kIA3IRQ9].init("IA3IRQ9", 0x0B69, 12, 0x000);
163 mRegisterValue[kIA3IRQA].init("IA3IRQA", 0x0B6A, 12, 0x000);
164 mRegisterValue[kIA3IRQB].init("IA3IRQB", 0x0B6B, 12, 0x000);
165 mRegisterValue[kIA3IRQC].init("IA3IRQC", 0x0B6C, 12, 0x000);
166 mRegisterValue[kIRQSW3].init("IRQSW3", 0x0B6D, 13, 0x1FFF);
167 mRegisterValue[kIRQHW3].init("IRQHW3", 0x0B6E, 13, 0x0000);
168 mRegisterValue[kIRQHL3].init("IRQHL3", 0x0B6F, 13, 0x0000);
169 mRegisterValue[kCTGDINI].init("CTGDINI", 0x0B80, 32, 0x00000000); // Global Counter/Timer
170 mRegisterValue[kCTGCTRL].init("CTGCTRL", 0x0B81, 12, 0xE3F);
171 mRegisterValue[kC08CPU0].init("C08CPU0", 0x0C00, 32, 0x00000000); // CPU constants
172 mRegisterValue[kC09CPU0].init("C09CPU0", 0x0C01, 32, 0x00000000);
173 mRegisterValue[kC10CPU0].init("C10CPU0", 0x0C02, 32, 0x00000000);
174 mRegisterValue[kC11CPU0].init("C11CPU0", 0x0C03, 32, 0x00000000);
175 mRegisterValue[kC12CPUA].init("C12CPUA", 0x0C04, 32, 0x00000000);
176 mRegisterValue[kC13CPUA].init("C13CPUA", 0x0C05, 32, 0x00000000);
177 mRegisterValue[kC14CPUA].init("C14CPUA", 0x0C06, 32, 0x00000000);
178 mRegisterValue[kC15CPUA].init("C15CPUA", 0x0C07, 32, 0x00000000);
179 mRegisterValue[kC08CPU1].init("C08CPU1", 0x0C08, 32, 0x00000000);
180 mRegisterValue[kC09CPU1].init("C09CPU1", 0x0C09, 32, 0x00000000);
181 mRegisterValue[kC10CPU1].init("C10CPU1", 0x0C0A, 32, 0x00000000);
182 mRegisterValue[kC11CPU1].init("C11CPU1", 0x0C0B, 32, 0x00000000);
183 mRegisterValue[kC08CPU2].init("C08CPU2", 0x0C10, 32, 0x00000000);
184 mRegisterValue[kC09CPU2].init("C09CPU2", 0x0C11, 32, 0x00000000);
185 mRegisterValue[kC10CPU2].init("C10CPU2", 0x0C12, 32, 0x00000000);
186 mRegisterValue[kC11CPU2].init("C11CPU2", 0x0C13, 32, 0x00000000);
187 mRegisterValue[kC08CPU3].init("C08CPU3", 0x0C18, 32, 0x00000000);
188 mRegisterValue[kC09CPU3].init("C09CPU3", 0x0C19, 32, 0x00000000);
189 mRegisterValue[kC10CPU3].init("C10CPU3", 0x0C1A, 32, 0x00000000);
190 mRegisterValue[kC11CPU3].init("C11CPU3", 0x0C1B, 32, 0x00000000);
191 mRegisterValue[kNMOD].init("NMOD", 0x0D40, 6, 0x08); // NI intermace
192 mRegisterValue[kNDLY].init("NDLY", 0x0D41, 30, 0x24924924);
193 mRegisterValue[kNED].init("NED", 0x0D42, 16, 0xA240);
194 mRegisterValue[kNTRO].init("NTRO", 0x0D43, 18, 0x3FFFC);
195 mRegisterValue[kNRRO].init("NRRO", 0x0D44, 18, 0x3FFFC);
196 mRegisterValue[kNES].init("NES", 0x0D45, 32, 0x00000000);
197 mRegisterValue[kNTP].init("NTP", 0x0D46, 32, 0x0000FFFF);
198 mRegisterValue[kNBND].init("NBND", 0x0D47, 16, 0x6020);
199 mRegisterValue[kNP0].init("NP0", 0x0D48, 11, 0x44C);
200 mRegisterValue[kNP1].init("NP1", 0x0D49, 11, 0x44C);
201 mRegisterValue[kNP2].init("NP2", 0x0D4A, 11, 0x44C);
202 mRegisterValue[kNP3].init("NP3", 0x0D4B, 11, 0x44C);
203 mRegisterValue[kNCUT].init("NCUT", 0x0D4C, 32, 0xFFFFFFFF);
204 mRegisterValue[kTPPT0].init("TPPT0", 0x3000, 7, 0x01); // Filter and Preprocessor
205 mRegisterValue[kTPFS].init("TPFS", 0x3001, 7, 0x05);
206 mRegisterValue[kTPFE].init("TPFE", 0x3002, 7, 0x14);
207 mRegisterValue[kTPPGR].init("TPPGR", 0x3003, 7, 0x15);
208 mRegisterValue[kTPPAE].init("TPPAE", 0x3004, 7, 0x1E);
209 mRegisterValue[kTPQS0].init("TPQS0", 0x3005, 7, 0x00);
210 mRegisterValue[kTPQE0].init("TPQE0", 0x3006, 7, 0x0A);
211 mRegisterValue[kTPQS1].init("TPQS1", 0x3007, 7, 0x0B);
212 mRegisterValue[kTPQE1].init("TPQE1", 0x3008, 7, 0x14);
213 mRegisterValue[kEBD].init("EBD", 0x3009, 3, 0x0);
214 mRegisterValue[kEBAQA].init("EBAQA", 0x300A, 7, 0x00);
215 mRegisterValue[kEBSIA].init("EBSIA", 0x300B, 7, 0x20);
216 mRegisterValue[kEBSF].init("EBSF", 0x300C, 1, 0x1);
217 mRegisterValue[kEBSIM].init("EBSIM", 0x300D, 1, 0x1);
218 mRegisterValue[kEBPP].init("EBPP", 0x300E, 1, 0x1);
219 mRegisterValue[kEBPC].init("EBPC", 0x300F, 1, 0x1);
220 mRegisterValue[kEBIS].init("EBIS", 0x3014, 10, 0x005);
221 mRegisterValue[kEBIT].init("EBIT", 0x3015, 12, 0x028);
222 mRegisterValue[kEBIL].init("EBIL", 0x3016, 8, 0xF0);
223 mRegisterValue[kEBIN].init("EBIN", 0x3017, 1, 0x1);
224 mRegisterValue[kFLBY].init("FLBY", 0x3018, 1, 0x0);
225 mRegisterValue[kFPBY].init("FPBY", 0x3019, 1, 0x0);
226 mRegisterValue[kFGBY].init("FGBY", 0x301A, 1, 0x0);
227 mRegisterValue[kFTBY].init("FTBY", 0x301B, 1, 0x0);
228 mRegisterValue[kFCBY].init("FCBY", 0x301C, 1, 0x0);
229 mRegisterValue[kFPTC].init("FPTC", 0x3020, 2, 0x3);
230 mRegisterValue[kFPNP].init("FPNP", 0x3021, 9, 0x078);
231 mRegisterValue[kFPCL].init("FPCL", 0x3022, 1, 0x1);
232 mRegisterValue[kFGTA].init("FGTA", 0x3028, 12, 0x014);
233 mRegisterValue[kFGTB].init("FGTB", 0x3029, 12, 0x80C);
234 mRegisterValue[kFGCL].init("FGCL", 0x302A, 1, 0x1);
235 mRegisterValue[kFTAL].init("FTAL", 0x3030, 10, 0x0F6);
236 mRegisterValue[kFTLL].init("FTLL", 0x3031, 9, 0x11D);
237 mRegisterValue[kFTLS].init("FTLS", 0x3032, 9, 0x0D3);
238 mRegisterValue[kFCW1].init("FCW1", 0x3038, 8, 0x1E);
239 mRegisterValue[kFCW2].init("FCW2", 0x3039, 8, 0xD4);
240 mRegisterValue[kFCW3].init("FCW3", 0x303A, 8, 0xE6);
241 mRegisterValue[kFCW4].init("FCW4", 0x303B, 8, 0x4A);
242 mRegisterValue[kFCW5].init("FCW5", 0x303C, 8, 0xEF);
243 mRegisterValue[kTPFP].init("TPFP", 0x3040, 9, 0x037);
244 mRegisterValue[kTPHT].init("TPHT", 0x3041, 14, 0x00A0);
245 mRegisterValue[kTPVT].init("TPVT", 0x3042, 6, 0x00);
246 mRegisterValue[kTPVBY].init("TPVBY", 0x3043, 1, 0x0);
247 mRegisterValue[kTPCT].init("TPCT", 0x3044, 5, 0x08);
248 mRegisterValue[kTPCL].init("TPCL", 0x3045, 5, 0x01);
249 mRegisterValue[kTPCBY].init("TPCBY", 0x3046, 1, 0x1);
250 mRegisterValue[kTPD].init("TPD", 0x3047, 4, 0xF);
251 mRegisterValue[kTPCI0].init("TPCI0", 0x3048, 5, 0x00);
252 mRegisterValue[kTPCI1].init("TPCI1", 0x3049, 5, 0x00);
253 mRegisterValue[kTPCI2].init("TPCI2", 0x304A, 5, 0x00);
254 mRegisterValue[kTPCI3].init("TPCI3", 0x304B, 5, 0x00);
255 mRegisterValue[kADCMSK].init("ADCMSK", 0x3050, 21, 0x1FFFFF);
256 mRegisterValue[kADCINB].init("ADCINB", 0x3051, 2, 0x2);
257 mRegisterValue[kADCDAC].init("ADCDAC", 0x3052, 5, 0x10);
258 mRegisterValue[kADCPAR].init("ADCPAR", 0x3053, 18, 0x195EF);
259 mRegisterValue[kADCTST].init("ADCTST", 0x3054, 2, 0x0);
260 mRegisterValue[kSADCAZ].init("SADCAZ", 0x3055, 1, 0x1);
261 mRegisterValue[kFGF0].init("FGF0", 0x3080, 9, 0x000);
262 mRegisterValue[kFGF1].init("FGF1", 0x3081, 9, 0x000);
263 mRegisterValue[kFGF2].init("FGF2", 0x3082, 9, 0x000);
264 mRegisterValue[kFGF3].init("FGF3", 0x3083, 9, 0x000);
265 mRegisterValue[kFGF4].init("FGF4", 0x3084, 9, 0x000);
266 mRegisterValue[kFGF5].init("FGF5", 0x3085, 9, 0x000);
267 mRegisterValue[kFGF6].init("FGF6", 0x3086, 9, 0x000);
268 mRegisterValue[kFGF7].init("FGF7", 0x3087, 9, 0x000);
269 mRegisterValue[kFGF8].init("FGF8", 0x3088, 9, 0x000);
270 mRegisterValue[kFGF9].init("FGF9", 0x3089, 9, 0x000);
271 mRegisterValue[kFGF10].init("FGF10", 0x308A, 9, 0x000);
272 mRegisterValue[kFGF11].init("FGF11", 0x308B, 9, 0x000);
273 mRegisterValue[kFGF12].init("FGF12", 0x308C, 9, 0x000);
274 mRegisterValue[kFGF13].init("FGF13", 0x308D, 9, 0x000);
275 mRegisterValue[kFGF14].init("FGF14", 0x308E, 9, 0x000);
276 mRegisterValue[kFGF15].init("FGF15", 0x308F, 9, 0x000);
277 mRegisterValue[kFGF16].init("FGF16", 0x3090, 9, 0x000);
278 mRegisterValue[kFGF17].init("FGF17", 0x3091, 9, 0x000);
279 mRegisterValue[kFGF18].init("FGF18", 0x3092, 9, 0x000);
280 mRegisterValue[kFGF19].init("FGF19", 0x3093, 9, 0x000);
281 mRegisterValue[kFGF20].init("FGF20", 0x3094, 9, 0x000);
282 mRegisterValue[kFGA0].init("FGA0", 0x30A0, 6, 0x00);
283 mRegisterValue[kFGA1].init("FGA1", 0x30A1, 6, 0x00);
284 mRegisterValue[kFGA2].init("FGA2", 0x30A2, 6, 0x00);
285 mRegisterValue[kFGA3].init("FGA3", 0x30A3, 6, 0x00);
286 mRegisterValue[kFGA4].init("FGA4", 0x30A4, 6, 0x00);
287 mRegisterValue[kFGA5].init("FGA5", 0x30A5, 6, 0x00);
288 mRegisterValue[kFGA6].init("FGA6", 0x30A6, 6, 0x00);
289 mRegisterValue[kFGA7].init("FGA7", 0x30A7, 6, 0x00);
290 mRegisterValue[kFGA8].init("FGA8", 0x30A8, 6, 0x00);
291 mRegisterValue[kFGA9].init("FGA9", 0x30A9, 6, 0x00);
292 mRegisterValue[kFGA10].init("FGA10", 0x30AA, 6, 0x00);
293 mRegisterValue[kFGA11].init("FGA11", 0x30AB, 6, 0x00);
294 mRegisterValue[kFGA12].init("FGA12", 0x30AC, 6, 0x00);
295 mRegisterValue[kFGA13].init("FGA13", 0x30AD, 6, 0x00);
296 mRegisterValue[kFGA14].init("FGA14", 0x30AE, 6, 0x00);
297 mRegisterValue[kFGA15].init("FGA15", 0x30AF, 6, 0x00);
298 mRegisterValue[kFGA16].init("FGA16", 0x30B0, 6, 0x00);
299 mRegisterValue[kFGA17].init("FGA17", 0x30B1, 6, 0x00);
300 mRegisterValue[kFGA18].init("FGA18", 0x30B2, 6, 0x00);
301 mRegisterValue[kFGA19].init("FGA19", 0x30B3, 6, 0x00);
302 mRegisterValue[kFGA20].init("FGA20", 0x30B4, 6, 0x00);
303 mRegisterValue[kFLL00].init("FLL00", 0x3100, 6, 0x00); // non-linearity table, 64 x 6 bits
304 mRegisterValue[kFLL01].init("FLL01", 0x3101, 6, 0x00);
305 mRegisterValue[kFLL02].init("FLL02", 0x3102, 6, 0x00);
306 mRegisterValue[kFLL03].init("FLL03", 0x3103, 6, 0x00);
307 mRegisterValue[kFLL04].init("FLL04", 0x3104, 6, 0x00);
308 mRegisterValue[kFLL05].init("FLL05", 0x3105, 6, 0x00);
309 mRegisterValue[kFLL06].init("FLL06", 0x3106, 6, 0x00);
310 mRegisterValue[kFLL07].init("FLL07", 0x3107, 6, 0x00);
311 mRegisterValue[kFLL08].init("FLL08", 0x3108, 6, 0x00);
312 mRegisterValue[kFLL09].init("FLL09", 0x3109, 6, 0x00);
313 mRegisterValue[kFLL0A].init("FLL0A", 0x310A, 6, 0x00);
314 mRegisterValue[kFLL0B].init("FLL0B", 0x310B, 6, 0x00);
315 mRegisterValue[kFLL0C].init("FLL0C", 0x310C, 6, 0x00);
316 mRegisterValue[kFLL0D].init("FLL0D", 0x310D, 6, 0x00);
317 mRegisterValue[kFLL0E].init("FLL0E", 0x310E, 6, 0x00);
318 mRegisterValue[kFLL0F].init("FLL0F", 0x310F, 6, 0x00);
319 mRegisterValue[kFLL10].init("FLL10", 0x3110, 6, 0x00);
320 mRegisterValue[kFLL11].init("FLL11", 0x3111, 6, 0x00);
321 mRegisterValue[kFLL12].init("FLL12", 0x3112, 6, 0x00);
322 mRegisterValue[kFLL13].init("FLL13", 0x3113, 6, 0x00);
323 mRegisterValue[kFLL14].init("FLL14", 0x3114, 6, 0x00);
324 mRegisterValue[kFLL15].init("FLL15", 0x3115, 6, 0x00);
325 mRegisterValue[kFLL16].init("FLL16", 0x3116, 6, 0x00);
326 mRegisterValue[kFLL17].init("FLL17", 0x3117, 6, 0x00);
327 mRegisterValue[kFLL18].init("FLL18", 0x3118, 6, 0x00);
328 mRegisterValue[kFLL19].init("FLL19", 0x3119, 6, 0x00);
329 mRegisterValue[kFLL1A].init("FLL1A", 0x311A, 6, 0x00);
330 mRegisterValue[kFLL1B].init("FLL1B", 0x311B, 6, 0x00);
331 mRegisterValue[kFLL1C].init("FLL1C", 0x311C, 6, 0x00);
332 mRegisterValue[kFLL1D].init("FLL1D", 0x311D, 6, 0x00);
333 mRegisterValue[kFLL1E].init("FLL1E", 0x311E, 6, 0x00);
334 mRegisterValue[kFLL1F].init("FLL1F", 0x311F, 6, 0x00);
335 mRegisterValue[kFLL20].init("FLL20", 0x3120, 6, 0x00);
336 mRegisterValue[kFLL21].init("FLL21", 0x3121, 6, 0x00);
337 mRegisterValue[kFLL22].init("FLL22", 0x3122, 6, 0x00);
338 mRegisterValue[kFLL23].init("FLL23", 0x3123, 6, 0x00);
339 mRegisterValue[kFLL24].init("FLL24", 0x3124, 6, 0x00);
340 mRegisterValue[kFLL25].init("FLL25", 0x3125, 6, 0x00);
341 mRegisterValue[kFLL26].init("FLL26", 0x3126, 6, 0x00);
342 mRegisterValue[kFLL27].init("FLL27", 0x3127, 6, 0x00);
343 mRegisterValue[kFLL28].init("FLL28", 0x3128, 6, 0x00);
344 mRegisterValue[kFLL29].init("FLL29", 0x3129, 6, 0x00);
345 mRegisterValue[kFLL2A].init("FLL2A", 0x312A, 6, 0x00);
346 mRegisterValue[kFLL2B].init("FLL2B", 0x312B, 6, 0x00);
347 mRegisterValue[kFLL2C].init("FLL2C", 0x312C, 6, 0x00);
348 mRegisterValue[kFLL2D].init("FLL2D", 0x312D, 6, 0x00);
349 mRegisterValue[kFLL2E].init("FLL2E", 0x312E, 6, 0x00);
350 mRegisterValue[kFLL2F].init("FLL2F", 0x312F, 6, 0x00);
351 mRegisterValue[kFLL30].init("FLL30", 0x3130, 6, 0x00);
352 mRegisterValue[kFLL31].init("FLL31", 0x3131, 6, 0x00);
353 mRegisterValue[kFLL32].init("FLL32", 0x3132, 6, 0x00);
354 mRegisterValue[kFLL33].init("FLL33", 0x3133, 6, 0x00);
355 mRegisterValue[kFLL34].init("FLL34", 0x3134, 6, 0x00);
356 mRegisterValue[kFLL35].init("FLL35", 0x3135, 6, 0x00);
357 mRegisterValue[kFLL36].init("FLL36", 0x3136, 6, 0x00);
358 mRegisterValue[kFLL37].init("FLL37", 0x3137, 6, 0x00);
359 mRegisterValue[kFLL38].init("FLL38", 0x3138, 6, 0x00);
360 mRegisterValue[kFLL39].init("FLL39", 0x3139, 6, 0x00);
361 mRegisterValue[kFLL3A].init("FLL3A", 0x313A, 6, 0x00);
362 mRegisterValue[kFLL3B].init("FLL3B", 0x313B, 6, 0x00);
363 mRegisterValue[kFLL3C].init("FLL3C", 0x313C, 6, 0x00);
364 mRegisterValue[kFLL3D].init("FLL3D", 0x313D, 6, 0x00);
365 mRegisterValue[kFLL3E].init("FLL3E", 0x313E, 6, 0x00);
366 mRegisterValue[kFLL3F].init("FLL3F", 0x313F, 6, 0x00);
367 mRegisterValue[kPASADEL].init("PASADEL", 0x3158, 8, 0xFF); // end om non-lin table
368 mRegisterValue[kPASAPHA].init("PASAPHA", 0x3159, 6, 0x3F);
369 mRegisterValue[kPASAPRA].init("PASAPRA", 0x315A, 6, 0x0F);
370 mRegisterValue[kPASADAC].init("PASADAC", 0x315B, 8, 0x80);
371 mRegisterValue[kPASACHM].init("PASACHM", 0x315C, 19, 0x7FFFF);
372 mRegisterValue[kPASASTL].init("PASASTL", 0x315D, 8, 0xFF);
373 mRegisterValue[kPASAPR1].init("PASAPR1", 0x315E, 1, 0x0);
374 mRegisterValue[kPASAPR0].init("PASAPR0", 0x315F, 1, 0x0);
375 mRegisterValue[kSADCTRG].init("SADCTRG", 0x3161, 1, 0x0);
376 mRegisterValue[kSADCRUN].init("SADCRUN", 0x3162, 1, 0x0);
377 mRegisterValue[kSADCPWR].init("SADCPWR", 0x3163, 3, 0x7);
378 mRegisterValue[kL0TSIM].init("L0TSIM", 0x3165, 14, 0x0050);
379 mRegisterValue[kSADCEC].init("SADCEC", 0x3166, 7, 0x00);
380 mRegisterValue[kSADCMC].init("SADCMC", 0x3170, 8, 0xC0);
381 mRegisterValue[kSADCOC].init("SADCOC", 0x3171, 8, 0x19);
382 mRegisterValue[kSADCGTB].init("SADCGTB", 0x3172, 32, 0x37737700);
383 mRegisterValue[kSEBDEN].init("SEBDEN", 0x3178, 3, 0x0);
384 mRegisterValue[kSEBDOU].init("SEBDOU", 0x3179, 3, 0x0);
385 mRegisterValue[kTPL00].init("TPL00", 0x3180, 5, 0x00); // pos table, 128 x 5 bits
386 mRegisterValue[kTPL01].init("TPL01", 0x3181, 5, 0x00);
387 mRegisterValue[kTPL02].init("TPL02", 0x3182, 5, 0x00);
388 mRegisterValue[kTPL03].init("TPL03", 0x3183, 5, 0x00);
389 mRegisterValue[kTPL04].init("TPL04", 0x3184, 5, 0x00);
390 mRegisterValue[kTPL05].init("TPL05", 0x3185, 5, 0x00);
391 mRegisterValue[kTPL06].init("TPL06", 0x3186, 5, 0x00);
392 mRegisterValue[kTPL07].init("TPL07", 0x3187, 5, 0x00);
393 mRegisterValue[kTPL08].init("TPL08", 0x3188, 5, 0x00);
394 mRegisterValue[kTPL09].init("TPL09", 0x3189, 5, 0x00);
395 mRegisterValue[kTPL0A].init("TPL0A", 0x318A, 5, 0x00);
396 mRegisterValue[kTPL0B].init("TPL0B", 0x318B, 5, 0x00);
397 mRegisterValue[kTPL0C].init("TPL0C", 0x318C, 5, 0x00);
398 mRegisterValue[kTPL0D].init("TPL0D", 0x318D, 5, 0x00);
399 mRegisterValue[kTPL0E].init("TPL0E", 0x318E, 5, 0x00);
400 mRegisterValue[kTPL0F].init("TPL0F", 0x318F, 5, 0x00);
401 mRegisterValue[kTPL10].init("TPL10", 0x3190, 5, 0x00);
402 mRegisterValue[kTPL11].init("TPL11", 0x3191, 5, 0x00);
403 mRegisterValue[kTPL12].init("TPL12", 0x3192, 5, 0x00);
404 mRegisterValue[kTPL13].init("TPL13", 0x3193, 5, 0x00);
405 mRegisterValue[kTPL14].init("TPL14", 0x3194, 5, 0x00);
406 mRegisterValue[kTPL15].init("TPL15", 0x3195, 5, 0x00);
407 mRegisterValue[kTPL16].init("TPL16", 0x3196, 5, 0x00);
408 mRegisterValue[kTPL17].init("TPL17", 0x3197, 5, 0x00);
409 mRegisterValue[kTPL18].init("TPL18", 0x3198, 5, 0x00);
410 mRegisterValue[kTPL19].init("TPL19", 0x3199, 5, 0x00);
411 mRegisterValue[kTPL1A].init("TPL1A", 0x319A, 5, 0x00);
412 mRegisterValue[kTPL1B].init("TPL1B", 0x319B, 5, 0x00);
413 mRegisterValue[kTPL1C].init("TPL1C", 0x319C, 5, 0x00);
414 mRegisterValue[kTPL1D].init("TPL1D", 0x319D, 5, 0x00);
415 mRegisterValue[kTPL1E].init("TPL1E", 0x319E, 5, 0x00);
416 mRegisterValue[kTPL1F].init("TPL1F", 0x319F, 5, 0x00);
417 mRegisterValue[kTPL20].init("TPL20", 0x31A0, 5, 0x00);
418 mRegisterValue[kTPL21].init("TPL21", 0x31A1, 5, 0x00);
419 mRegisterValue[kTPL22].init("TPL22", 0x31A2, 5, 0x00);
420 mRegisterValue[kTPL23].init("TPL23", 0x31A3, 5, 0x00);
421 mRegisterValue[kTPL24].init("TPL24", 0x31A4, 5, 0x00);
422 mRegisterValue[kTPL25].init("TPL25", 0x31A5, 5, 0x00);
423 mRegisterValue[kTPL26].init("TPL26", 0x31A6, 5, 0x00);
424 mRegisterValue[kTPL27].init("TPL27", 0x31A7, 5, 0x00);
425 mRegisterValue[kTPL28].init("TPL28", 0x31A8, 5, 0x00);
426 mRegisterValue[kTPL29].init("TPL29", 0x31A9, 5, 0x00);
427 mRegisterValue[kTPL2A].init("TPL2A", 0x31AA, 5, 0x00);
428 mRegisterValue[kTPL2B].init("TPL2B", 0x31AB, 5, 0x00);
429 mRegisterValue[kTPL2C].init("TPL2C", 0x31AC, 5, 0x00);
430 mRegisterValue[kTPL2D].init("TPL2D", 0x31AD, 5, 0x00);
431 mRegisterValue[kTPL2E].init("TPL2E", 0x31AE, 5, 0x00);
432 mRegisterValue[kTPL2F].init("TPL2F", 0x31AF, 5, 0x00);
433 mRegisterValue[kTPL30].init("TPL30", 0x31B0, 5, 0x00);
434 mRegisterValue[kTPL31].init("TPL31", 0x31B1, 5, 0x00);
435 mRegisterValue[kTPL32].init("TPL32", 0x31B2, 5, 0x00);
436 mRegisterValue[kTPL33].init("TPL33", 0x31B3, 5, 0x00);
437 mRegisterValue[kTPL34].init("TPL34", 0x31B4, 5, 0x00);
438 mRegisterValue[kTPL35].init("TPL35", 0x31B5, 5, 0x00);
439 mRegisterValue[kTPL36].init("TPL36", 0x31B6, 5, 0x00);
440 mRegisterValue[kTPL37].init("TPL37", 0x31B7, 5, 0x00);
441 mRegisterValue[kTPL38].init("TPL38", 0x31B8, 5, 0x00);
442 mRegisterValue[kTPL39].init("TPL39", 0x31B9, 5, 0x00);
443 mRegisterValue[kTPL3A].init("TPL3A", 0x31BA, 5, 0x00);
444 mRegisterValue[kTPL3B].init("TPL3B", 0x31BB, 5, 0x00);
445 mRegisterValue[kTPL3C].init("TPL3C", 0x31BC, 5, 0x00);
446 mRegisterValue[kTPL3D].init("TPL3D", 0x31BD, 5, 0x00);
447 mRegisterValue[kTPL3E].init("TPL3E", 0x31BE, 5, 0x00);
448 mRegisterValue[kTPL3F].init("TPL3F", 0x31BF, 5, 0x00);
449 mRegisterValue[kTPL40].init("TPL40", 0x31C0, 5, 0x00);
450 mRegisterValue[kTPL41].init("TPL41", 0x31C1, 5, 0x00);
451 mRegisterValue[kTPL42].init("TPL42", 0x31C2, 5, 0x00);
452 mRegisterValue[kTPL43].init("TPL43", 0x31C3, 5, 0x00);
453 mRegisterValue[kTPL44].init("TPL44", 0x31C4, 5, 0x00);
454 mRegisterValue[kTPL45].init("TPL45", 0x31C5, 5, 0x00);
455 mRegisterValue[kTPL46].init("TPL46", 0x31C6, 5, 0x00);
456 mRegisterValue[kTPL47].init("TPL47", 0x31C7, 5, 0x00);
457 mRegisterValue[kTPL48].init("TPL48", 0x31C8, 5, 0x00);
458 mRegisterValue[kTPL49].init("TPL49", 0x31C9, 5, 0x00);
459 mRegisterValue[kTPL4A].init("TPL4A", 0x31CA, 5, 0x00);
460 mRegisterValue[kTPL4B].init("TPL4B", 0x31CB, 5, 0x00);
461 mRegisterValue[kTPL4C].init("TPL4C", 0x31CC, 5, 0x00);
462 mRegisterValue[kTPL4D].init("TPL4D", 0x31CD, 5, 0x00);
463 mRegisterValue[kTPL4E].init("TPL4E", 0x31CE, 5, 0x00);
464 mRegisterValue[kTPL4F].init("TPL4F", 0x31CF, 5, 0x00);
465 mRegisterValue[kTPL50].init("TPL50", 0x31D0, 5, 0x00);
466 mRegisterValue[kTPL51].init("TPL51", 0x31D1, 5, 0x00);
467 mRegisterValue[kTPL52].init("TPL52", 0x31D2, 5, 0x00);
468 mRegisterValue[kTPL53].init("TPL53", 0x31D3, 5, 0x00);
469 mRegisterValue[kTPL54].init("TPL54", 0x31D4, 5, 0x00);
470 mRegisterValue[kTPL55].init("TPL55", 0x31D5, 5, 0x00);
471 mRegisterValue[kTPL56].init("TPL56", 0x31D6, 5, 0x00);
472 mRegisterValue[kTPL57].init("TPL57", 0x31D7, 5, 0x00);
473 mRegisterValue[kTPL58].init("TPL58", 0x31D8, 5, 0x00);
474 mRegisterValue[kTPL59].init("TPL59", 0x31D9, 5, 0x00);
475 mRegisterValue[kTPL5A].init("TPL5A", 0x31DA, 5, 0x00);
476 mRegisterValue[kTPL5B].init("TPL5B", 0x31DB, 5, 0x00);
477 mRegisterValue[kTPL5C].init("TPL5C", 0x31DC, 5, 0x00);
478 mRegisterValue[kTPL5D].init("TPL5D", 0x31DD, 5, 0x00);
479 mRegisterValue[kTPL5E].init("TPL5E", 0x31DE, 5, 0x00);
480 mRegisterValue[kTPL5F].init("TPL5F", 0x31DF, 5, 0x00);
481 mRegisterValue[kTPL60].init("TPL60", 0x31E0, 5, 0x00);
482 mRegisterValue[kTPL61].init("TPL61", 0x31E1, 5, 0x00);
483 mRegisterValue[kTPL62].init("TPL62", 0x31E2, 5, 0x00);
484 mRegisterValue[kTPL63].init("TPL63", 0x31E3, 5, 0x00);
485 mRegisterValue[kTPL64].init("TPL64", 0x31E4, 5, 0x00);
486 mRegisterValue[kTPL65].init("TPL65", 0x31E5, 5, 0x00);
487 mRegisterValue[kTPL66].init("TPL66", 0x31E6, 5, 0x00);
488 mRegisterValue[kTPL67].init("TPL67", 0x31E7, 5, 0x00);
489 mRegisterValue[kTPL68].init("TPL68", 0x31E8, 5, 0x00);
490 mRegisterValue[kTPL69].init("TPL69", 0x31E9, 5, 0x00);
491 mRegisterValue[kTPL6A].init("TPL6A", 0x31EA, 5, 0x00);
492 mRegisterValue[kTPL6B].init("TPL6B", 0x31EB, 5, 0x00);
493 mRegisterValue[kTPL6C].init("TPL6C", 0x31EC, 5, 0x00);
494 mRegisterValue[kTPL6D].init("TPL6D", 0x31ED, 5, 0x00);
495 mRegisterValue[kTPL6E].init("TPL6E", 0x31EE, 5, 0x00);
496 mRegisterValue[kTPL6F].init("TPL6F", 0x31EF, 5, 0x00);
497 mRegisterValue[kTPL70].init("TPL70", 0x31F0, 5, 0x00);
498 mRegisterValue[kTPL71].init("TPL71", 0x31F1, 5, 0x00);
499 mRegisterValue[kTPL72].init("TPL72", 0x31F2, 5, 0x00);
500 mRegisterValue[kTPL73].init("TPL73", 0x31F3, 5, 0x00);
501 mRegisterValue[kTPL74].init("TPL74", 0x31F4, 5, 0x00);
502 mRegisterValue[kTPL75].init("TPL75", 0x31F5, 5, 0x00);
503 mRegisterValue[kTPL76].init("TPL76", 0x31F6, 5, 0x00);
504 mRegisterValue[kTPL77].init("TPL77", 0x31F7, 5, 0x00);
505 mRegisterValue[kTPL78].init("TPL78", 0x31F8, 5, 0x00);
506 mRegisterValue[kTPL79].init("TPL79", 0x31F9, 5, 0x00);
507 mRegisterValue[kTPL7A].init("TPL7A", 0x31FA, 5, 0x00);
508 mRegisterValue[kTPL7B].init("TPL7B", 0x31FB, 5, 0x00);
509 mRegisterValue[kTPL7C].init("TPL7C", 0x31FC, 5, 0x00);
510 mRegisterValue[kTPL7D].init("TPL7D", 0x31FD, 5, 0x00);
511 mRegisterValue[kTPL7E].init("TPL7E", 0x31FE, 5, 0x00);
512 mRegisterValue[kTPL7F].init("TPL7F", 0x31FF, 5, 0x00);
513 mRegisterValue[kMEMRW].init("MEMRW", 0xD000, 7, 0x79); // end om pos table
514 mRegisterValue[kMEMCOR].init("MEMCOR", 0xD001, 9, 0x000);
515 mRegisterValue[kDMDELA].init("DMDELA", 0xD002, 4, 0x8);
516 mRegisterValue[kDMDELS].init("DMDELS", 0xD003, 4, 0x8);
517}
518
519void TrapConfig::resetRegs()
520{
521 // Reset the content om all TRAP registers to the reset values (see TRAP User Manual)
522
523 for (int iReg = 0; iReg < kLastReg; iReg++) {
524 mRegisterValue[iReg].reset();
525 }
526}
527
528void TrapConfig::resetDmem()
529{
530 // reset the data memory
531
532 for (int iAddr = 0; iAddr < mgkDmemWords; iAddr++) {
533 mDmem[iAddr].reset();
534 }
535}
536
537int TrapConfig::getTrapReg(TrapReg_t reg, int det, int rob, int mcm)
538{
539 // get the value of an individual TRAP register
540 // if it is individual for TRAPs a valid TRAP has to be specified
541
542 if ((reg < 0) || (reg >= kLastReg)) {
543 LOG(error) << "Non-existing register requested";
544 return 0;
545 } else {
546 return mRegisterValue[reg].getValue(det, rob, mcm);
547 }
548}
549
550bool TrapConfig::setTrapReg(TrapReg_t reg, int value, int det)
551{
552 // set a value for the given TRAP register on all chambers,
553
554 return mRegisterValue[reg].setValue(value, det);
555}
556
557bool TrapConfig::setTrapReg(TrapReg_t reg, int value, int det, int rob, int mcm)
558{
559 // set the value for the given TRAP register of an individual MCM
560
561 return mRegisterValue[reg].setValue(value, det, rob, mcm);
562}
563
564unsigned int TrapConfig::peek(int addr, int det, int rob, int mcm)
565{
566 // reading from given address
567
568 if ((addr >= mgkDmemStartAddress) &&
569 (addr < (mgkDmemStartAddress + mgkDmemWords))) {
570 return getDmemUnsigned(addr, det, rob, mcm);
571 } else {
572 TrapReg_t mcmReg = getRegByAddress(addr);
573 if (mcmReg >= 0 && mcmReg < kLastReg) {
574 return (unsigned int)getTrapReg(mcmReg, det, rob, mcm);
575 }
576 }
577
578 LOG(error) << "peek for invalid addr: 0x" << hex << setw(4) << addr;
579 return 0;
580}
581
582bool TrapConfig::poke(int addr, unsigned int value, int det, int rob, int mcm)
583{
584 // writing to given address
585
586 if ((addr >= mgkDmemStartAddress) &&
587 (addr < (mgkDmemStartAddress + mgkDmemWords))) {
588 LOG(debug1) << "DMEM 0x" << hex << setw(8) << addr << ": " << dec << value;
589 return setDmem(addr, value, det, rob, mcm);
590 } else {
591 TrapReg_t mcmReg = getRegByAddress(addr);
592 if (mcmReg >= 0 && mcmReg < kLastReg) {
593 LOG(debug1) << "Register: " << getRegName(mcmReg) << " : " << value;
594 return setTrapReg(mcmReg, (unsigned int)value, det, rob, mcm);
595 }
596 }
597
598 LOG(error) << "poke for invalid address: 0x" << hex << setw(4) << addr;
599 return false;
600}
601
602bool TrapConfig::setDmemAlloc(int addr, Alloc_t mode)
603{
604 addr = addr - mgkDmemStartAddress;
605
606 if (addr < 0 || addr >= mgkDmemWords) {
607 LOG(error) << "Invalid DMEM address: 0x%04x" << hex << std::setw(4) << addr + mgkDmemStartAddress;
608 return false;
609 } else {
610 mDmem[addr].allocate(mode);
611 return true;
612 }
613}
614
615bool TrapConfig::setDmem(int addr, unsigned int value, int det)
616{
617 // set the content of the given DMEM address
618
619 addr = addr - mgkDmemStartAddress;
620
621 if (addr < 0 || addr >= mgkDmemWords) {
622 LOG(error) << "No DMEM address: 0x" << hex << std::setw(8) << addr + mgkDmemStartAddress;
623 return false;
624 }
625
626 if (!mDmem[addr].setValue(value, det)) {
627 LOG(error) << "Problem writing to DMEM address 0x" << hex << std::setw(4) << addr;
628 return false;
629 } else {
630 return true;
631 }
632}
633
634bool TrapConfig::setDmem(int addr, unsigned int value, int det, int rob, int mcm)
635{
636 // set the content of the given DMEM address
637 addr = addr - mgkDmemStartAddress;
638
639 if (addr < 0 || addr >= mgkDmemWords) {
640 LOG(error) << "No DMEM address: 0x" << hex << std::setw(8) << addr + mgkDmemStartAddress;
641 return false;
642 }
643
644 if (!mDmem[addr].setValue(value, det, rob, mcm)) {
645 LOG(error) << "Problem writing to DMEM address 0x" << hex << std::setw(4) << addr;
646 return false;
647 } else {
648 return true;
649 }
650}
651
652unsigned int TrapConfig::getDmemUnsigned(int addr, int det, int rob, int mcm)
653{
654 // get the content of the data memory at the given address
655 // (only if the value is the same for all MCMs)
656
657 addr = addr - mgkDmemStartAddress;
658
659 if (addr < 0 || addr >= mgkDmemWords) {
660 LOG(error) << "No DMEM address: 0x" << hex << std::setw(8) << addr + mgkDmemStartAddress;
661 return 0;
662 }
663
664 return mDmem[addr].getValue(det, rob, mcm);
665}
666
667bool TrapConfig::printTrapReg(TrapReg_t reg, int det, int rob, int mcm)
668{
669 // print the value stored in the given register
670 // if it is individual a valid MCM has to be specified
671
672 if ((det >= 0 && det < MAXCHAMBER) &&
673 (rob >= 0 && rob < NROBC1) &&
674 (mcm >= 0 && mcm < NMCMROB + 2)) {
675 LOG(info) << getRegName((TrapReg_t)reg) << "(" << std::setw(2) << getRegNBits((TrapReg_t)reg)
676 << " bits) at 0x" << hex << std::setw(4) << getRegAddress((TrapReg_t)reg)
677 << " is 0x" << hex << std::setw(8) << mRegisterValue[reg].getValue(det, rob, mcm)
678 << " and resets to: 0x" << hex << std::setw(8) << getRegResetValue((TrapReg_t)reg)
679 << " (currently individual mode)";
680 } else {
681 LOG(error) << "Register value is MCM-specific: Invalid detector, ROB or MCM requested";
682 return false;
683 }
684
685 return true;
686}
687
688bool TrapConfig::printTrapAddr(int addr, int det, int rob, int mcm)
689{
690 // print the value stored at the given address in the MCM chip
691 TrapReg_t reg = getRegByAddress(addr);
692 if (reg >= 0 && reg < kLastReg) {
693 return printTrapReg(reg, det, rob, mcm);
694 } else {
695 LOG(error) << "There is no register at address 0x" << hex << setw(8) << addr << " in the simulator";
696 return false;
697 }
698}
699
700TrapConfig::TrapReg_t TrapConfig::getRegByAddress(int address)
701{
702 // get register by its address
703 // used for reading of configuration data as sent to real FEE
704
705 if (address < mgkRegisterAddressBlockStart[0]) {
706 return kLastReg;
707 } else if (address < mgkRegisterAddressBlockStart[0] + mgkRegisterAddressBlockSize[0]) {
708 return mgRegAddressMap[address - mgkRegisterAddressBlockStart[0]];
709 } else if (address < mgkRegisterAddressBlockStart[1]) {
710 return kLastReg;
711 } else if (address < mgkRegisterAddressBlockStart[1] + mgkRegisterAddressBlockSize[1]) {
712 return mgRegAddressMap[address - mgkRegisterAddressBlockStart[1] + mgkRegisterAddressBlockSize[0]];
713 } else if (address < mgkRegisterAddressBlockStart[2]) {
714 return kLastReg;
715 } else if (address < mgkRegisterAddressBlockStart[2] + mgkRegisterAddressBlockSize[2]) {
716 return mgRegAddressMap[address - mgkRegisterAddressBlockStart[2] + mgkRegisterAddressBlockSize[1] + mgkRegisterAddressBlockSize[0]];
717 } else {
718 return kLastReg;
719 }
720}
721
722void TrapConfig::printMemDatx(ostream& os, int addr)
723{
724 // print the content of the data memory as datx
725
726 printMemDatx(os, addr, 0, 0, 127);
727}
728
729void TrapConfig::printMemDatx(ostream& os, int addr, int det, int rob, int mcm)
730{
731 // print the content of the data memory as datx
732
733 if (addr < mgkDmemStartAddress || addr >= mgkDmemStartAddress + mgkDmemWords) {
734 LOG(error) << "Invalid DMEM address 0x" << hex << setw(8) << addr;
735 return;
736 }
737 printDatx(os, addr, getDmemUnsigned(addr, det, rob, mcm), rob, mcm);
738}
739
740void TrapConfig::printMemDatx(ostream& os, TrapReg_t reg)
741{
742 // print the content of the data memory as datx
743
744 printMemDatx(os, reg, 0, 0, 127);
745}
746
747void TrapConfig::printMemDatx(ostream& os, TrapReg_t reg, int det, int rob, int mcm)
748{
749 // print the content of the data memory as datx
750
751 if (reg >= kLastReg) {
752 LOG(error) << "Invalid register " << dec << reg;
753 return;
754 }
755 printDatx(os, getRegAddress(reg), getTrapReg(reg, det, rob, mcm), rob, mcm);
756}
757
758void TrapConfig::printDatx(ostream& os, unsigned int addr, unsigned int data, int rob, int mcm)
759{
760 // print the value at the given address as datx
761
762 os << std::setw(5) << 10
763 << std::setw(8) << addr
764 << std::setw(12) << data;
765 if (mcm == 127) {
766 os << std::setw(8) << 127;
767 } else {
768 os << std::setw(8) << FeeParam::aliToExtAli(rob, mcm);
769 }
770
771 os << std::endl;
772}
773
774void TrapConfig::printVerify(ostream& os, int det, int rob, int mcm)
775{
776 // print verification file in datx format
777
778 for (int iReg = 0; iReg < kLastReg; ++iReg) {
779 os << std::setw(5) << 9
780 << std::setw(8) << getRegAddress((TrapReg_t)iReg)
781 << std::setw(12) << getTrapReg((TrapReg_t)iReg, det, rob, mcm)
782 << std::setw(8) << FeeParam::aliToExtAli(rob, mcm)
783 << std::endl;
784 }
785
786 for (int iWord = 0; iWord < mgkDmemWords; ++iWord) {
787 if (getDmemUnsigned(mgkDmemStartAddress + iWord, det, rob, mcm) == 0) {
788 continue;
789 }
790 os << std::setw(5) << 9
791 << std::setw(8) << mgkDmemStartAddress + iWord
792 << std::setw(12) << getDmemUnsigned(mgkDmemStartAddress + iWord, det, rob, mcm)
793 << std::setw(8) << FeeParam::aliToExtAli(rob, mcm)
794 << std::endl;
795 }
796}
797
798TrapConfig::TrapValue::TrapValue() : mAllocMode(kAllocGlobal)
799{
800 mData.resize(1);
801 mValid.resize(1);
802 mData[0] = 0;
803 mValid[0] = true;
804}
805
806bool TrapConfig::TrapValue::allocate(Alloc_t alloc)
807{
808 // allocate memory for the specified granularity
809 mAllocMode = alloc;
810 int mSize = mgkSize[mAllocMode];
811
812 if (mSize > 0) {
813 mData.resize(mSize);
814 mValid.resize(mSize);
815 for (int i = 0; i < mSize; ++i) {
816 mData[i] = 0;
817 mValid[i] = false;
818 }
819 }
820
821 return true;
822}
823
824// this exists purely to read in from ocdb to ccdb, and get around a root dictionary error of Alloc_t
825bool TrapConfig::TrapValue::allocatei(int alloc)
826{
827 // allocate memory for the specified granularity
828 mAllocMode = (Alloc_t)alloc;
829 int mSize = mgkSize[mAllocMode];
830 //cout << "in allocatei : with alloc = " << alloc << " and mSize is now :" << mSize << endl;
831 if (mSize > 0) {
832 mData.resize(mSize);
833 mValid.resize(mSize);
834 for (int i = 0; i < mSize; ++i) {
835 mData[i] = 0;
836 mValid[i] = false;
837 }
838 }
839
840 return true;
841}
842
843int TrapConfig::TrapValue::getIdx(int det, int rob, int mcm)
844{
845 // return Idx to access the data for the given position
846
847 int idx = -1;
848
849 switch (mAllocMode) {
850 case kAllocNone:
851 idx = -1;
852 break;
853 case kAllocGlobal:
854 idx = 0;
855 break;
856 case kAllocByDetector:
857 idx = det;
858 break;
859 case kAllocByHC:
860 idx = det + (rob % 2);
861 break;
862 case kAllocByMCM:
863 idx = 18 * 8 * det + 18 * rob + mcm;
864 break;
865 case kAllocByLayer:
866 idx = det % 6;
867 break;
868 case kAllocByMCMinSM:
869 idx = 18 * 8 * (det % 30) + 18 * rob + mcm;
870 break;
871 default:
872 idx = -1;
873 LOG(error) << "Invalid allocation mode";
874 }
875 if (idx < mData.size()) {
876 // LOG(info) << "Index ok " << dec << idx << " (size " << mData.size() << ") for " << this->getName() << " getIdx : " << det <<"::"<< rob<< "::" << mcm << "::" << mAllocMode;
877 return idx;
878 } else {
879 LOG(warn) << "Index too large " << dec << idx << " (size " << mData.size() << ") for "
880 << " getIdx : " << det << "::" << rob << "::" << mcm << "::" << mAllocMode;
881 return -1;
882 }
883}
884
885bool TrapConfig::TrapValue::setData(unsigned int value)
886{
887 // set the given value everywhere
888
889 for (int i = 0; i < mData.size(); ++i) {
890 mData[i] = value;
891 mValid[i] = false;
892 }
893
894 return true;
895}
896
897bool TrapConfig::TrapValue::setData(unsigned int value, int det)
898{
899 // set the data for a given detector
900
901 int idx = getIdx(det, 0, 0);
902
903 if (idx >= 0) {
904 // short cut for detector-wise allocation
905 if (mAllocMode == kAllocByDetector) {
906 if (mValid[idx] && (mData[idx] != value)) {
907 LOG(debug) << "Overwriting previous value " << dec << mData[idx] << " of "
908 << " with " << value << " for " << det;
909 }
910 mData[idx] = value;
911 mValid[idx] = true;
912 return true;
913 } else {
914 for (int rob = 0; rob < 8; ++rob) {
915 for (int mcm = 0; mcm < 18; ++mcm) {
916 idx = getIdx(det, rob, mcm);
917 if (mValid[idx] && (mData[idx] != value)) {
918 LOG(debug) << "Overwriting previous value " << mData[idx] << " of "
919 << " with " << value << " for " << det << " " << rob << ":" << setw(2) << mcm;
920 }
921 mData[idx] = value;
922 mValid[idx] = true;
923 }
924 }
925 return true;
926 }
927 }
928
929 if (mAllocMode == kAllocNone) {
930 // assume nobody cares
931 return true;
932 }
933 return false;
934}
935
936bool TrapConfig::TrapValue::setData(unsigned int value, int det, int rob, int mcm)
937{
938 // set data for an individual MCM
939
940 int idx = getIdx(det, rob, mcm);
941
942 if (idx >= 0) {
943 if (mValid[idx] && (mData[idx] != value)) {
944 LOG(debug) << "Overwriting previous value " << mData[idx] << " of "
945 << " with " << value << " " << det << ":" << rob << std::setw(2) << mcm << " (idx: " << idx << ")";
946 }
947 mData[idx] = value;
948 mValid[idx] = true;
949 return true;
950 } else if (mAllocMode == kAllocNone) {
951 return true;
952 } else {
953 LOG(error) << Form("setting failed");
954 return false;
955 }
956}
957
958unsigned int TrapConfig::TrapValue::getData(int det, int rob, int mcm)
959{
960 // read data for the given MCM
961
962 int idx = getIdx(det, rob, mcm);
963 if (idx >= 0) {
964 if (!mValid[idx]) {
965 LOG(debug1) << "reading from unwritten address: "
966 << " at idx " << idx << ":" << mValid[idx];
967 }
968 return mData[idx];
969 } else {
970 LOG(error) << "read from invalid address";
971 return 0;
972 }
973}
974
975TrapConfig::TrapRegister::TrapRegister() : TrapValue(), mName("invalid"), mAddr(0), mNbits(0), mResetValue(0)
976{
977 // default constructor
978}
979
980TrapConfig::TrapRegister::~TrapRegister() = default;
981
982void TrapConfig::TrapRegister::init(const char* name, int addr, int nBits, int resetValue)
983{
984 // init the TRAP register
985
986 if (mAddr == 0) {
987 mName = name;
988 mAddr = addr;
989 mNbits = nBits;
990 mResetValue = resetValue;
991 } else {
992 LOG(fatal) << "Re-initialising an existing TRAP register ";
993 }
994}
995
996void TrapConfig::TrapRegister::initfromrun2(const char* name, int addr, int nBits, int resetValue)
997{
998 // init the TRAP register
999
1000 mName = name;
1001 mAddr = addr;
1002 mNbits = nBits;
1003 mResetValue = resetValue;
1004 //LOG(fatal) << "Re-initialising an existing TRAP register " << name << ":" << mName << " : " << addr << ":" << mAddr << " : " << nBits << ":" << mNbits << " : " << resetValue << ":" << mResetValue;
1005 //LOG(fatal) << "Re-initialising an existing TRAP register";
1006}
1007
1008void TrapConfig::PrintDmemValue3(TrapConfig::TrapDmemWord* trapval, std::ofstream& output)
1009{
1010 output << "\t AllocationMode : " << trapval->getAllocMode() << std::endl;
1011 output << "\t Array size : " << trapval->getDataSize() << std::endl;
1012 for (int dataarray = 0; dataarray < trapval->getDataSize(); dataarray++) {
1013 output << "\t " << trapval->getDataRaw(dataarray) << " : valid : " << trapval->getValidRaw(dataarray) << std::endl;
1014 }
1015}
1016
1017void TrapConfig::PrintRegisterValue3(TrapConfig::TrapRegister* trapval, std::ofstream& output)
1018{
1019 output << "\t AllocationMode : " << trapval->getAllocMode() << std::endl;
1020 output << "\t Array size : " << trapval->getDataSize() << std::endl;
1021 for (int dataarray = 0; dataarray < trapval->getDataSize(); dataarray++) {
1022 output << "\t " << trapval->getDataRaw(dataarray) << " : valid : " << trapval->getValidRaw(dataarray) << std::endl;
1023 }
1024}
1025
1026void TrapConfig::DumpTrapConfig2File(std::string filename)
1027{
1028 std::ofstream outfile(filename);
1029 outfile << "Trap Registers : " << std::endl;
1030 for (int regvalue = 0; regvalue < TrapConfig::kLastReg; regvalue++) {
1031 outfile << " Trap : " << mRegisterValue[regvalue].getName()
1032 << " at : 0x " << std::hex << mRegisterValue[regvalue].getAddr() << std::dec
1033 << " with nbits : " << mRegisterValue[regvalue].getNbits()
1034 << " and reset value of : " << mRegisterValue[regvalue].getResetValue() << std::endl;
1035 // now for the inherited AliTRDtrapValue members;
1036 PrintRegisterValue3(&mRegisterValue[regvalue], outfile);
1037 }
1038
1039 // outfile << "done with regiser values now for dmemwords" << std::endl;
1040 outfile << "DMEM Words : " << std::endl;
1041 for (int dmemwords = 0; dmemwords < TrapConfig::mgkDmemWords; dmemwords++) {
1042 // copy fName, fAddr
1043 // inherited from trapvalue : fAllocMode, fSize fData and fValid
1044 // trapconfig->mDmem[dmemwords].mName= run2config->fDmem[dmemwords].fName; // this gets set on setting the address
1045 outfile << "Name : " << mDmem[dmemwords].getName() << " :address : " << mDmem[dmemwords].getAddress() << std::endl;
1046 PrintDmemValue3(&mDmem[dmemwords], outfile);
1047 }
1048}
1049
1050void TrapConfig::configureOnlineGains()
1051{
1052 // we dont want to do this anymore .... but here for future reference.
1053 /* if (hasOnlineFilterGain()) {
1054 const int nDets = MAXCHAMBER;
1055 const int nMcms = Geometry::MCMmax();
1056 const int nChs = Geometry::ADCmax();
1057
1058 for (int ch = 0; ch < nChs; ++ch) {
1059 TrapConfig::TrapReg_t regFGAN = (TrapConfig::TrapReg_t)(TrapConfig::kFGA0 + ch);
1060 TrapConfig::TrapReg_t regFGFN = (TrapConfig::TrapReg_t)(TrapConfig::kFGF0 + ch);
1061 mTrapConfig->setTrapRegAlloc(regFGAN, TrapConfig::kAllocByMCM);
1062 mTrapConfig->setTrapRegAlloc(regFGFN, TrapConfig::kAllocByMCM);
1063 }
1064
1065 for (int iDet = 0; iDet < nDets; ++iDet) {
1066 //const int MaxRows = Geometry::getStack(iDet) == 2 ? NROWC0 : NROWC1;
1067 int MaxCols = NCOLUMN;
1068 //CalOnlineGainTableROC gainTbl = mGainTable.getGainTableROC(iDet);
1069 const int nRobs = Geometry::getStack(iDet) == 2 ? Geometry::ROBmaxC0() : Geometry::ROBmaxC1();
1070
1071 for (int rob = 0; rob < nRobs; ++rob) {
1072 for (int mcm = 0; mcm < nMcms; ++mcm) {
1073 // for (int row = 0; row < MaxRows; row++) {
1074 // for (int col = 0; col < MaxCols; col++) {
1075 //TODO set ADC reference voltage
1076 mTrapConfig->setTrapReg(TrapConfig::kADCDAC, mTrapConfig.getAdcdacrm(iDet, rob, mcm), iDet, rob, mcm);
1077
1078 // set constants channel-wise
1079 for (int ch = 0; ch < nChs; ++ch) {
1080 TrapConfig::TrapReg_t regFGAN = (TrapConfig::TrapReg_t)(TrapConfig::kFGA0 + ch);
1081 TrapConfig::TrapReg_t regFGFN = (TrapConfig::TrapReg_t)(TrapConfig::kFGF0 + ch);
1082 mTrapConfig->setTrapReg(regFGAN, mTrapConfig.getFGANrm(iDet, rob, mcm, ch), iDet, rob, mcm); //TODO can put these internal to TrapConfig
1083 mTrapConfig->setTrapReg(regFGFN, mTrapConfig.getFGFNrm(iDet, rob, mcm, ch), iDet, rob, mcm);
1084 }
1085 }
1086 // }
1087 // }
1088 }
1089 }
1090 }*/
1091}
mcm
uint16_t mcm
Definition CompressedHeader.h:1
rob
uint16_t rob
Definition CompressedHeader.h:2
Constants.h
Global TRD definitions and constants.
i
int32_t i
Definition GPUCommonAlgorithm.h:443
output
void output(const std::map< std::string, ChannelStat > &channels)
Definition rawdump.cxx:197
debug
std::ostringstream debug
Definition VariantJSONHelpers.h:307
o2::trd::FeeParam::aliToExtAli
static unsigned int aliToExtAli(int rob, int aliid)
Definition FeeParam.cxx:225
o2::trd::TrapConfig::TrapRegister::initfromrun2
void initfromrun2(const char *name, int addr, int nBits, int resetValue)
Definition TrapConfig.cxx:996
o2::trd::TrapConfig::TrapRegister::init
void init(const char *name, int addr, int nBits, int resetValue)
Definition TrapConfig.cxx:982
o2::trd::TrapConfig::TrapValue::getValidRaw
unsigned int getValidRaw(int i)
Definition TrapConfig.h:576
o2::trd::TrapConfig::TrapValue::mgkSize
static const std::array< int, TrapConfig::mlastAlloc > mgkSize
Definition TrapConfig.h:37
o2::trd::TrapConfig::TrapValue::getDataRaw
unsigned int getDataRaw(int i)
Definition TrapConfig.h:575
o2::trd::TrapConfig::TrapValue::setData
bool setData(unsigned int value)
Definition TrapConfig.cxx:885
o2::trd::TrapConfig::TrapValue::getData
unsigned int getData(int det, int rob, int mcm)
Definition TrapConfig.cxx:958
o2::trd::TrapConfig::TrapValue::getIdx
int getIdx(int det, int rob, int mcm)
Definition TrapConfig.cxx:843
o2::trd::TrapConfig::mDmem
std::array< TrapDmemWord, mgkDmemWords > mDmem
Definition TrapConfig.h:669
o2::trd::TrapConfig::PrintDmemValue3
void PrintDmemValue3(TrapConfig::TrapDmemWord *trapval, std::ofstream &output)
Definition TrapConfig.cxx:1008
o2::trd::TrapConfig::printTrapAddr
bool printTrapAddr(int addr, int det=-1, int rob=-1, int mcm=-1)
Definition TrapConfig.cxx:688
o2::trd::TrapConfig::peek
unsigned int peek(int addr, int det, int rob, int mcm)
Definition TrapConfig.cxx:564
o2::trd::TrapConfig::getRegNBits
unsigned short getRegNBits(TrapReg_t reg)
Definition TrapConfig.h:528
o2::trd::TrapConfig::printDatx
void printDatx(std::ostream &os, unsigned int addr, unsigned int data, int rob, int mcm)
Definition TrapConfig.cxx:758
o2::trd::TrapConfig::getRegAddress
unsigned short getRegAddress(TrapReg_t reg)
Definition TrapConfig.h:527
o2::trd::TrapConfig::poke
bool poke(int addr, unsigned int value, int det, int rob, int mcm)
Definition TrapConfig.cxx:582
o2::trd::TrapConfig::setDmem
bool setDmem(int addr, unsigned int value, int det)
Definition TrapConfig.cxx:615
o2::trd::TrapConfig::mgkDmemStartAddress
static const int mgkDmemStartAddress
Definition TrapConfig.h:544
o2::trd::TrapConfig::getDmemUnsigned
unsigned int getDmemUnsigned(int addr, int det, int rob, int mcm)
Definition TrapConfig.cxx:652
o2::trd::TrapConfig::getRegName
std::string getRegName(TrapReg_t reg)
Definition TrapConfig.h:526
o2::trd::TrapConfig::mgkRegisterAddressBlockSize
const std::array< int, 3 > mgkRegisterAddressBlockSize
Definition TrapConfig.h:677
o2::trd::TrapConfig::PrintRegisterValue3
void PrintRegisterValue3(TrapConfig::TrapRegister *trapval, std::ofstream &output)
Definition TrapConfig.cxx:1017
o2::trd::TrapConfig::getRegResetValue
unsigned int getRegResetValue(TrapReg_t reg)
Definition TrapConfig.h:529
o2::trd::TrapConfig::setTrapReg
bool setTrapReg(TrapReg_t reg, int value, int det)
Definition TrapConfig.cxx:550
o2::trd::TrapConfig::mgkRegisterAddressBlockStart
const std::array< int, 3 > mgkRegisterAddressBlockStart
Definition TrapConfig.h:676
o2::trd::TrapConfig::setDmemAlloc
bool setDmemAlloc(int addr, Alloc_t mode)
Definition TrapConfig.cxx:602
o2::trd::TrapConfig::mRegisterValue
std::array< TrapRegister, kLastReg > mRegisterValue
Definition TrapConfig.h:666
o2::trd::TrapConfig::getTrapReg
int getTrapReg(TrapReg_t reg, int det=-1, int rob=-1, int mcm=-1)
Definition TrapConfig.cxx:537
o2::trd::TrapConfig::printMemDatx
void printMemDatx(std::ostream &os, int addr)
Definition TrapConfig.cxx:722
o2::trd::TrapConfig::mgRegAddressMap
std::array< TrapReg_t, 0x400+0x200+0x4 > mgRegAddressMap
Definition TrapConfig.h:674
o2::trd::TrapConfig::printVerify
void printVerify(std::ostream &os, int det, int rob, int mcm)
Definition TrapConfig.cxx:774
o2::trd::TrapConfig::getRegByAddress
TrapReg_t getRegByAddress(int address)
Definition TrapConfig.cxx:700
o2::trd::TrapConfig::mgkDmemWords
static const int mgkDmemWords
Definition TrapConfig.h:545
o2::trd::TrapConfig::printTrapReg
bool printTrapReg(TrapReg_t reg, int det=-1, int rob=-1, int mcm=-1)
Definition TrapConfig.cxx:667
o2::trd::TrapConfig::mgRegAddressMapInitialized
static bool mgRegAddressMapInitialized
Definition TrapConfig.h:673
o2::trd::TrapConfig::DumpTrapConfig2File
void DumpTrapConfig2File(std::string filename)
Definition TrapConfig.cxx:1026
mode
GLenum mode
Definition glcorearb.h:266
address
GLuint GLuint64EXT address
Definition glcorearb.h:5846
name
GLuint const GLchar * name
Definition glcorearb.h:781
value
GLsizei const GLfloat * value
Definition glcorearb.h:819
data
GLboolean * data
Definition glcorearb.h:298
o2::trd::constants::NROBC1
constexpr int NROBC1
the number of ROBs per C1 chamber
Definition Constants.h:51
o2::trd::constants::NMCMROB
constexpr int NMCMROB
the number of MCMs per ROB
Definition Constants.h:46
o2::trd::constants::MAXCHAMBER
constexpr int MAXCHAMBER
the maximum number of installed chambers
Definition Constants.h:30
std
Defining DataPointCompositeObject explicitly as copiable.
Definition CcdbObjectInfo.h:121
filename
std::string filename()
Definition o2FairMQHeaderSizeTest.cxx:55
LOG
LOG(info)<< "Compressed in "<< sw.CpuTime()<< " s"